Add Zbs single-bit operations implementation (RV32, SystemVerilog) - #191
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jeff-7 wants to merge 35 commits into
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Add Zbs single-bit operations implementation (RV32, SystemVerilog)#191jeff-7 wants to merge 35 commits into
jeff-7 wants to merge 35 commits into
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🔧 DE1-SoC Synthesis Report Summary Diff
Comparing synthesis results from main branch vs. this PR |
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Thanks for the PR! Let us merge #190 first, so that you can use the |
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| // Zbs: Single-Bit Operations (RV32) | ||
| // | ||
| // Implements: | ||
| // - bclr / bclri | ||
| // - bset / bseti | ||
| // - binv / binvi | ||
| // - bext / bexti | ||
| // | ||
| // Design note: | ||
| // - Purely combinational ALU block | ||
| // - reg2[4:0] used as bit index | ||
| // - R/I distinction handled in decoder | ||
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for the documentation here I would just specify the section of the specification that corresponds to Zbs extension
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Just merged #190 , please rebase onto latest main so you can use |
Add Zbs instruction testbench with assertions and randomized tests
Refractor Zbs to use ALU enum types and Update testbench accordingly.
(migrate b_alu_control)
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hey @Dazhou-20383 i brought this up to date a bit. since we've released the integration for B extension already, we need to implement the Zbs decoder as part of this PR to make sure it works with the rest of the core |
…ix small lint issues
…tbench accordingly
TheDeepestSpace
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hey that looks great! i think you should be able to enable Zbs in the RISCOF config now so that it also run the tests on these instructions.
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Implements RV32 Zbs single-bit operations:
Design follows abstract ALU pattern: